Reference 1
Blocks without memory are called combinational; the output of a combinational block depends only on the current input.
Can be defined by truth table, boolean algebra.
Decoders: n-bit input -> 2^n outputs
Multiplexors: a selector: output is one of the inputs that is selected by a control.
Sequential logic is logic including state. In blocks with memory, the outputs can depends on both the inputs and the value stored in memory, which is called the state of the logic block.
Any logic can be implemented with only AND, OR, and NOT functions.
Any logic function can be written in a canonical form, where every input is either a true or complemented variable and there are only two levels of gates – one being AND and the other OR – with a possible inversion on the final output. ==> such a representation is called a two level representation.
Two forms:
Sum-of-products: a logical sum (OR) of products (AND)
Products-of-sums: the opposite.
cite: https://www.sciencedirect.com/topics/computer-science/register-transfer-level
“The register transfer level of modeling circuits in VHDL for use with register transfer level synthesis. Register transfer level is a level of description of a digital design in which the clocked behavior of the design is expressly described in terms of data transfers between storage elements in sequential logic, which may be implied, and combinatorial logic, which may represent any computing or arithmetic-logic-unit logic. RTL modeling allows design hierarchy that represents a structural description of other RTL models.”
Q&A How does the simulator load the binary into the memory for execution? Reference 1 A memory object: Example system configurations in gem5/configs/: gem5/configs/boot/: for Full-System mode. rcS files. These files will be loaded by the simulator after Linux boots and are executed by the shell. gem5/configs/common/: Caches.py: example cache configuration. Options.py: a script to set a variety of options, such as number of CPUs system clock … CacheConfig.
Aug 29 ECE 401⁄201. Prof. Engin Ipek, Cornell from High school to Ph.D. Text book: Computer Arch: a quantitative approach, 6th ed. by John L. Hennessy, David A. Patterson. Org: building computer works; Arch: works faster; FSM design: finite state machine. TA: Ryan Wong; Muhammad Mehdi; 527 CSB office hr. Blackboard. Midterm Oct 29. Final Dec 19. Three verilog projects. Verilog design projects. expand on basic MIPS R3000 processor.
ARM on Gem5 References: Extending gem5 for ARM Run FreeBSD on gem5 ARM More Trustzone References: Intro to TrustZone Difference between SGX and TrustZone TrustZone Explained Dan Rosenberg, Reflections on Trusting TrustZone Normal world vs Secure World: Embeded OS vs Secure OS Context Switch normal world use SMC (secure monitor call) instruction to call secure world. ==> exception into the monitor mode (TrustZone kernel) Non-secure bit in Secure Configuration Register; Non-secure bit in the main memory;
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Reference: MIPS directives. Directives .set pop/push The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings. These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.
References: [1] TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V. NDSS, 201902. paper [2] XuanTie 910, Pingtouge (Honey Badger), 20190725. RISCV Terms Hart: Hardware thread. Spec 20191213, Page 2. More Attacks Reference1 A2: Analog Malicious Hardware Reference1 “In the open spaces of an already placed and routed design, we contruct a circuit that use capacitors to siphon charge from nearby wires as they transition between digital values.
Reference 1 Packages Reference 1 Connectable The Connectable type class defines the module mkConnection, which is used to connect a pair of related types. typeclass Connectable#(type a, type b); module mkConnection#(a x1, b x2)(Empty); endtypeclass Instances of typeclass to be connectable Get and Put instance Connectable#(Get#(a), Put#(a)); One put and another will get the element. Tuples instance Connectable#(Tuple2#(a, c), Tuple2#(b, d)) provisos (Connectable#(a, b), Connectable#(c, d)); This is used by ClientServer to connect the Get of Client to the Put of the Server and visa-versa.
Reference 1 HDL Languages Hardware description languages. Three elements seldom present in a PL: Concurrency. Representation of time. Representation of structure. Gate and hardware structure persist and have a state even if they are doing nothing. Verilog (1980s) -> Verilog 1.0 (1995) -> Verilog 2.0 (2001) -> Verilog 3.1a (System Verilog, 2005) Extended Verilog to system-level modeling. VHDL (Very High Speed Integrated Circuit) System C Usage: OVM, VMM, UVM System Verilog Object Oriented Programming
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References: Chisel Bootcamp Chisel教程汇总 Verilog vs Chisel Comparison Scala Based on Java Virtual Machine (JVM). Scala – .class – JVM Scala designed for Domain-Specific Language developers: can build your own language based on Scala. Chisel Type parameters class or function definition can have type paramters, in order to define class/functions with arbitrary types. e.g. the following defines a function myMux which
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?