System Verilog

Reference 1

HDL Languages

Hardware description languages. Three elements seldom present in a PL:

  • Concurrency.
  • Representation of time.
  • Representation of structure. Gate and hardware structure persist and have a state even if they are doing nothing.

Verilog (1980s) -> Verilog 1.0 (1995) -> Verilog 2.0 (2001) -> Verilog 3.1a (System Verilog, 2005)

Extended Verilog to system-level modeling.

VHDL (Very High Speed Integrated Circuit)

System C

Usage:

  • OVM, VMM, UVM

System Verilog

Object Oriented Programming

Static vs. Automatic

  • static: default. not destroyed after simulation function.
  • automatic: destroyed after function.
  • Verilog

    • Reference 1 Port vs Parameters Port: arguments/interfaces to other modules, contains input/output. Parameter: constants. Typically used to specify the width of variables and time delays; has default value; can be overwritten during module instantiation. Verilog Functions https://www.chipverify.com/verilog/verilog-functions For certain pieces of code to be repetitive and called multiple times within the RTL. function [automatic] [return_type] name ([port_list]); [statements] endfunction Starts with function, ends with endfunction. Should have at least one input.

  1. reference ↩
Created Feb 17, 2020 // Last Updated Oct 8, 2022

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