Beri ISA

Reference 1

Coprocessor 0: system control, MMU

Coprocessor 1: FPU.

Coprocessor 2: CHERI capability feature.

Smaller caches motivated by the performance trade-offs in the FPGA substrate, which provides comparatively high-speed main memory, as well as a desire for simpilicity.

Features omitted from MIPS 4000 ISA:

  • only 64-bit, no 32-bit addressing support;
  • only big endian support; no variable-endian features;
  • BERI is usually configured as a single-core, single-threaded processor; Multiprocessor (BERI1) and multithreading (BERI2) are experimental.

Modifications to the MIPS TLB model

Memory Caches

L1 cache

  • separate instruction and data; not coherent in BERI1 (BERI2 has coherent).

  • explicit CACHE instructions are needed to synchronize the instruction and data caches.

  • each L1 cache is 16K, direct-mapped, write-through, and physically indexed.

L2 cache

  • shared between instruction and data;
  • 64K, 4-way set associative, write-back, and physically indexed.

Reset Exception

BERI start from 0x9000,0000,4000,0000 on reset, pointing to the miniboot ROM.

FPU

Some MIPS R4000 instructions are omitted; some instructions from MIPS IV are added.

Selected additions from later MIPS ISA

required by common compiler toolchains and operating systems.

CP0 shadow registers: config1, config2, config3

  • config1, allows queries of cache layout properties; used by FreeBSD during CPU discovery to select cache management routines;
  • config2, ?
  • config3, used by FreeBSD to detect that the processor supports the “user local” register, which is used by the C runtime to hold a pointer to thread-local storage.

RDHWR instruction, read hardware register.

  1. reference ↩
Created Apr 1, 2020 // Last Updated May 18, 2021

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