O3 CPU

References:

Out of order CPU model loosely based on the Alpha 21264.

  • Fetch
    • Fetch instructions each cycle;
    • Create DynInst
    • Branch prediction
  • Decode
    • Decode instructions each cycle;
    • Early resolution of PC-relative unconditional branches
  • Rename
    • Rename instructions using a physical register file with a free list
    • Stall when no regs to rename to, or back-end resources have filled up
  • Issue/Execute/Writeback
    • Three stages combined in one stage, IEW, using execute() function
      • Dispatching instructions to the instruction queue
      • Telling the instruction queue to issue instruction
      • Executing and write back instructions
  • Commit
    • Commit instructions each cycle;
    • Handling any faults that the instructions may have caused;
    • Also handles redirecting the front-end in the case of a branch misprediction.

ISA dependence

The O3CPU has been designed to try to separate code that is ISA dependent and code that is ISA independent. The pipeline stages and resources are all mainly ISA independent, as well as the lower level CPU code.

The ISA dependent code:

  • AlphaO3CPU implements Alpha-specific functions, such as hardware return from error interrupt (hwrei()) or reading interrupt flags.

ISA independent code:

  • FullO3CPU, handles orchstrating all of the pipeline stages and handling other ISA-independent actions.

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Created Feb 16, 2022 // Last Updated Feb 17, 2022

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