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IRTranslator

Reference

Overview

This pass can be disabled according to LLVM selector type. There are three selector types: FastISel, GlobalISel, and SelectionDAG. Both FastISel and SelectionDAG do not use IRTranslator pass for ISel, but instead uses target dependent passes, such as MipsModuleDAGToDAGISel, Mips16DAGToDAGISel, MipsSEDAGToDAGISel, etc. see MipsPassConfig::addInstSelector() in llvm/lib/Target/Mips/MipsTargetMachine.cpp. Users can provide options to help LLVM determine the right selector type. The logic is programmed at TargetPassConfig::addCoreISelPasses() in llvm/lib/CodeGen/TargetPassConfig.cpp. GlobalISel is a framework aiming to be used to replace FastISel and SelectionDAG. More on GlobalISel.

IRTranslator pass is responsible for translating LLVM IR Function into a Generic MIR MachineFunction.

This is typically a direct translation but does occasionally get a bit more involved. For example,

%2 = add i32 %0, %1

becomes:

%2:_(s32) = G_ADD %0:_(s32), %1:_(s32)

and

call i32 @puts(i8* %cast210)

is translated according to the ABI rules of the target.

Translating Function Calls

IRTranslator also implements the ABI’s calling convention by lowering calls, returns, and arguments to the appropriate physical register usage and instruction sequences.

This is achieved using the CallLowering implementation.

Translating Constants

Constant operands are translated as a use of a virtual register that is defined by a G_CONSTANT or G_FCONSTANT instruction.

These instructions are placed in the entry block to allow them to be subject to the continuous CSE implementation (Machine Common Subexpression Elimination Pass)

Tracking the pass code

Pass Creation/Registration

TargetPassConfig::addCoreISelPasses()
-> addIRTranslator()
   -> MipsPassConfig::addIRTranslator()
      -> TargetPassConfig::addPass(new IRTranslator());

IRTranslator::runOnMachineFunction

Steps:

get the IR function for this MachineFunction. ??? already has a MachineFunction for this IR function?

// Algo:
//   CallLowering = MF.subtarget.getCallLowering()
//   F = MF.getParent()
//   MIRBuilder.reset(MF)
//   getMBB(F.getEntryBB())
//   CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
//   for each bb in F
//     getMBB(bb)
//     for each inst in bb
//       if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
//         report_fatal_error("Don't know how to translate input");
//   finalize()

IRTranslator::runOnMachineFunction()

bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
  MF = &CurMF;
  const Function &F = MF->getFunction();
  if (F.empty())
    return false;
  GISelCSEAnalysisWrapper &Wrapper =
      getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
  // Set the CSEConfig and run the analysis.
  GISelCSEInfo *CSEInfo = nullptr;
  TPC = &getAnalysis<TargetPassConfig>();
  bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
                       ? EnableCSEInIRTranslator
                       : TPC->isGISelCSEEnabled();

  if (EnableCSE) {
    EntryBuilder = std::make_unique<CSEMIRBuilder>(CurMF);
    CSEInfo = &Wrapper.get(TPC->getCSEConfig());
    EntryBuilder->setCSEInfo(CSEInfo);
    CurBuilder = std::make_unique<CSEMIRBuilder>(CurMF);
    CurBuilder->setCSEInfo(CSEInfo);
  } else {
    EntryBuilder = std::make_unique<MachineIRBuilder>();
    CurBuilder = std::make_unique<MachineIRBuilder>();
  }
  CLI = MF->getSubtarget().getCallLowering();
  CurBuilder->setMF(*MF);
  EntryBuilder->setMF(*MF);
  MRI = &MF->getRegInfo();
  DL = &F.getParent()->getDataLayout();
  ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
  FuncInfo.MF = MF;
  FuncInfo.BPI = nullptr;
  const auto &TLI = *MF->getSubtarget().getTargetLowering();
  const TargetMachine &TM = MF->getTarget();
  SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo);
  SL->init(TLI, TM, *DL);

  EnableOpts = TM.getOptLevel() != CodeGenOpt::None && !skipFunction(F);

  assert(PendingPHIs.empty() && "stale PHIs");

  if (!DL->isLittleEndian()) {
    // Currently we don't properly handle big endian code.
    OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                               F.getSubprogram(), &F.getEntryBlock());
    R << "unable to translate in big endian mode";
    reportTranslationError(*MF, *TPC, *ORE, R);
  }

  // Release the per-function state when we return, whether we succeeded or not.
  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });

  // Setup a separate basic-block for the arguments and constants
  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
  MF->push_back(EntryBB);
  EntryBuilder->setMBB(*EntryBB);

  DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHI()->getDebugLoc();
  SwiftError.setFunction(CurMF);
  SwiftError.createEntriesInEntryBlock(DbgLoc);

  // Create all blocks, in IR order, to preserve the layout.
  for (const BasicBlock &BB: F) {
    auto *&MBB = BBToMBB[&BB];

    MBB = MF->CreateMachineBasicBlock(&BB);
    MF->push_back(MBB);

    if (BB.hasAddressTaken())
      MBB->setHasAddressTaken();
    // Lele: should we pass a similar BB.getOwnershipInfo() -> MBB.setOwnershipInfo()?
  }

  // Make our arguments/constants entry block fallthrough to the IR entry block.
  EntryBB->addSuccessor(&getMBB(F.front()));

  // Lower the actual args into this basic block.
  SmallVector<ArrayRef<Register>, 8> VRegArgs;
  for (const Argument &Arg: F.args()) {
    if (DL->getTypeStoreSize(Arg.getType()) == 0)
      continue; // Don't handle zero sized types.
    ArrayRef<Register> VRegs = getOrCreateVRegs(Arg);
    VRegArgs.push_back(VRegs);

    if (Arg.hasSwiftErrorAttr()) {
      assert(VRegs.size() == 1 && "Too many vregs for Swift error");
      SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(), VRegs[0]);
    }
  }

  if (!CLI->lowerFormalArguments(*EntryBuilder.get(), F, VRegArgs)) {
    OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                               F.getSubprogram(), &F.getEntryBlock());
    R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
    reportTranslationError(*MF, *TPC, *ORE, R);
    return false;
  }

  // Need to visit defs before uses when translating instructions.
  GISelObserverWrapper WrapperObserver;
  if (EnableCSE && CSEInfo)
    WrapperObserver.addObserver(CSEInfo);
  {
    ReversePostOrderTraversal<const Function *> RPOT(&F);
#ifndef NDEBUG
    DILocationVerifier Verifier;
    WrapperObserver.addObserver(&Verifier);
#endif // ifndef NDEBUG
    RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
    for (const BasicBlock *BB : RPOT) {
      MachineBasicBlock &MBB = getMBB(*BB);
      // Set the insertion point of all the following translations to
      // the end of this basic block.
      CurBuilder->setMBB(MBB);
      HasTailCall = false;
      for (const Instruction &Inst : *BB) {
        // If we translated a tail call in the last step, then we know
        // everything after the call is either a return, or something that is
        // handled by the call itself. (E.g. a lifetime marker or assume
        // intrinsic.) In this case, we should stop translating the block and
        // move on.
        if (HasTailCall)
          break;
#ifndef NDEBUG
        Verifier.setCurrentInst(&Inst);
#endif // ifndef NDEBUG
        if (translate(Inst))
          continue;

        OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                                   Inst.getDebugLoc(), BB);
        R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);

        if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
          std::string InstStrStorage;
          raw_string_ostream InstStr(InstStrStorage);
          InstStr << Inst;

          R << ": '" << InstStr.str() << "'";
        }

        reportTranslationError(*MF, *TPC, *ORE, R);
        return false;
      }

      finalizeBasicBlock();
    }
#ifndef NDEBUG
    WrapperObserver.removeObserver(&Verifier);
#endif
  }

  finishPendingPhis();

  SwiftError.propagateVRegs();

  // Merge the argument lowering and constants block with its single
  // successor, the LLVM-IR entry block.  We want the basic block to
  // be maximal.
  assert(EntryBB->succ_size() == 1 &&
         "Custom BB used for lowering should have only one successor");
  // Get the successor of the current entry block.
  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
  assert(NewEntryBB.pred_size() == 1 &&
         "LLVM-IR entry block has a predecessor!?");
  // Move all the instruction from the current entry block to the
  // new entry block.
  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
                    EntryBB->end());

  // Update the live-in information for the new entry block.
  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
    NewEntryBB.addLiveIn(LiveIn);
  NewEntryBB.sortUniqueLiveIns();

  // Get rid of the now empty basic block.
  EntryBB->removeSuccessor(&NewEntryBB);
  MF->remove(EntryBB);
  MF->DeleteMachineBasicBlock(EntryBB);

  assert(&MF->front() == &NewEntryBB &&
         "New entry wasn't next in the list of basic block!");

  // Initialize stack protector information.
  StackProtector &SP = getAnalysis<StackProtector>();
  SP.copyToMachineFrameInfo(MF->getFrameInfo());

  return false;
}

A DenseMap<const BasicBlock *, MachineBasicBlock *> BBToMBB; store all BB->MBB.
- A one to one mapping.
MachineBasicBlock * MachineFunction::CreateMachineBasicBlock(const BasicBlock *bb)
Translate Instructions:IRTranslator::translateXXX()
- IRTranslator::translate()
- IRTranslator::translateLoad()
- IRTranslator::translateStore()
- IRTranslator::translateGetElementPtr()
- IRTranslator::translateMemFunc()
- IRTranslator::translateCall()
- IRTranslator::translateInvoke()
- IRTranslator::translateCallBr()
- IRTranslator::translateLandingPad()
- IRTranslator::translateInlineAsm()
- IRTranslator::translateAlloc()
- IRTranslator::translatePHI()
- IRTranslator::translateSimpleIntrinsic()
- ~ 37 funcs.

IRTranslator::translate()

The general algorithm:

Look for a virtual register for each operand or create one.
Update the VMap accordingly.
- Alternative: For constant arguments, if they are compile time constants, produce an immediate in the right operand and do not touch ValToVReg.
- In implementation: Actually we will go with a virtual register for each constants because it may be expensive to actually materialize the constant. Moreover, if the constant spans on several instructions, CSE may not catch them.
- Update ValToVReg and remember that we saw a constant in Constants. We will materialize all the constant in finalize.
Create the generic instruction.

Reference:

llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
``
```
// 
```

IRTranslator::translateLoad()

Call path

IRTranslator::runOnMachineFunction() -> IRTranslator::translate(Inst) -> IRTranslator::translateLoad(), via HANDLE_INST macro, and instruction definitions in llvm/IR/Instructions.def:

// IRTranslator::translate(const Instruction &Inst)

  switch (Inst.getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS)                                        \
  case Instruction::OPCODE:                                                    \
    return translate##OPCODE(Inst, *CurBuilder.get());
#include "llvm/IR/Instruction.def"
  default:
    return false;
  }

code IRTranslator::translateLoad()

If you could revise
the fundmental principles of
computer system design
to improve security...

... what would you change?