TLB.bsv

Q&A

  • How does TLB read/write permissions on page table? Can we add more bits for permission/types?

Reference 1 2

MIPS R4000 Basics

  • 48 TLB entries, each can map variable-sized pages from 4Kb to 16Mb.
  • Address translation value is tagged with the most-significant bits of its virtual address, and a per-process identifier.

Instruction TLB: a two-entry instruction TLB.s

Joint TLB: upon TLB miss, software will refill the JTLB from a page table resident in memory. This JTLB contains both data and instruction jointly. JTLB entry to be rewritten is selected at random.

mkTLB

Struct/State

TLBEntryLo, MIPS register

TLBEntryLo: describes the format of the EntryLo 0 & 1 CP0 register in MIPS, and also the two low records of each TLB entry.

Bits: 2 + 28 + 3 + x = 34-36 bits

Elements:

  • CHERI added: two cap permission bits: noCapStore, noCapLoad, to allow storing/loading capabilities on the tlb entry.
  • physical address of a page, 28 bits

  • cache algorithm, dirty bit, valid bit, global bit.

    // file: cheri/trunk/MIPS.bsv

// The TlbEntryLo type describes the format of the EntryLo 0 & 1 CP0 register in MIPS, and also the two low records
// of each TLB entry
typedef struct { 
`ifdef USECAP
Bool    noCapStore; // Allow storing capabilities
Bool    noCapLoad;  // Allow loading capabilities
`endif
//Bit#(28)  zeros;
Bit#(28)  pfn;  // Physical address of the page.
CacheCA   c;    // Cache algorithm or cache coherency attribute for multi-processor systems.
Bool      d;    // Dirty - True if writes are allowed.  Writes will cause exception otherwise.
Bool      v;    // Valid - If False, attempts to use this location cause an exception.
Bool      g;    // Global - If True this entry will match regardless of ASID.  Both "Lo(G)"s in an odd/even pair should be identical.
} TlbEntryLo deriving(Bits, Eq, FShow); // 34-36 bits

CachedTLBEntry:

// TLB.bsv

typedef struct {
  Bool        valid;
  Bit#(5)     whichLoBit; // Bit to check for which EntryLo to use, the MSB of the page mask.
  Bit#(1)     oddPage;    // Which page is cached.
  Bool        global;
  Bit#(12)    pageMask;
  TlbEntryHi  entryHi;
  TlbEntryLo  entryLo;
} CachedTLBEntry deriving (Bits, Eq);

Module mkTLB

module mkTLB#(Bit#(16) coreId)(TLBIfc ifc);

Interfaces

TLBIfc

interface TLBIfc;
  interface Server#(TLBEntryT, TLBEntryT) readWrite;
  interface Vector#(NumTLBLookups, TranslationIfc) lookup;
  method Action debugDump;
  method Action putConfig(Bit#(LogAssosTLBSize) tlbRandom, Bool largeTlb, Bit#(8) entryHiAsid);
endinterface

States:

3? lookups interfaces, each have its request(reqIn) and response() method.

lookups1 is used for lookup instruction in tlb;

lookups2 is used for lookup data in tlb;

  • Vector#(NumTLBLookups, TranslationIfc) lookups;
  • lookups [0] = interface TranslationIfc; // This is the TLB probe interface
  • lookups [i] = interface TranslationIfc;

rules

  • startTLB(tlbState == Serving);

  • initialize

  • doRead(tlbState == DoRead);

    • pick/dep the request from readWrite_fifo.first
    • read tlb entry from entryLo0 and entryLo1
    • store address as tlbAddr, and readOut_fifo.enq(tlbAddr)

  • doWrite(tlbState == DoWrite);

    • pick/dep the request from readWrite_fifo.first
    • choose and save write victim oldEnt. set tlbState <= WriteVictim
    • write tlb entry to entryLo0 and entryLo1

  • writeVictimOut(tlbState == WriteVictim);

    • randomIndex ???

  • readTLB(tlbState == Serving);

interface lookups[i]

i = 1, 2, …, < NumTLBLookups

canPut = (req_fifo[i].notFull);

request(TlbRequest reqIn)

guarded by canPut. CPU will wait until the req_fifo has space to insert new request.

Steps:

  • for xkphys, kseg1, kseg0, regions, use simple translation, not using page tables; ==> no page table permissions!!!
  • micro TLB hit? compare with last_hit[i][ti]
  • TLB search: req_fifos[i].enq(reqIn);
  • rule startTLB will consume the req_fifos[i]

response()

guarded by if (rsp_fifos[i].notEmpty). CPU will wait here until there is a response.

  1. github/beri. ↩
  2. MIPS R4000 manual. ↩
Created May 2, 2020 // Last Updated May 23, 2020

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