(ISAv7: Ch 7, p240)
Format
CSC cs, rt, offset(cb)
CSCR cs, rt(cb)
CSCI cs, offset(cb)
Capability register cs is stored at memory location [cb.base + cb.offset + rt + 16 * offset], and the bit in the tag memory associated with this address is set to the value of cs.tag.
Capability cb must contain a capability that grants permission to store capabilities. The virtual address of [cb.base + cb.offset + rt + 16 * offset] must be capability_size aligned.
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?