Verilog

Reference 1

Port vs Parameters

Port: arguments/interfaces to other modules, contains input/output.

Parameter: constants. Typically used to specify the width of variables and time delays; has default value; can be overwritten during module instantiation.

Verilog Functions

https://www.chipverify.com/verilog/verilog-functions

For certain pieces of code to be repetitive and called multiple times within the RTL.

function [automatic] [return_type] name ([port_list]);
    [statements]
endfunction

Starts with function, ends with endfunction.

Should have at least one input.

Return could be void (return nothing)

automatic will make the functino reentrant and items declared within the task are dynamically allocated rather than shared between different invocations of the task.

  • Useful for recursive functions
  • Useful when the same function is executed concurrently by N Processes when forked.

Function declarations


Verilog Modules

A Verilog module is a building block. It defines a design or testbench component. It does so by defining the building block’s ports and internal behaviour.

A module can be embedded into another module, creating hierachical designs.

Module & Components:

  • Starts with module and ends with endmodule
  • Identifier that is the name of the module
  • Optional list of parameters
  • Optional list of ports
  • Module item

Parameters

Allows a single piece of Verilog module code to be extensible and reusable.

Each instantiation of a Verilog module can supply different values to the parameters, creating different variations of the same base Verilog module.

For example, a FIFO Verilog module may have a Verilog parameter to adjust its data width (or even data type, in SystemVerilog).

Verilog Port

A list of Verilog port (port list).

To communicate with other modules.

Ways to communicate other than ports: backdoors.

Module item

Item is essentially the code inside a module.

After port declaration.

Defines what constitutes the module, and can include many different types of declarations and definitions.

  • nets,
  • variable declarations,
  • always blocks,
  • initial blocks,

Example

module my_module
#(
    parameter WIDTH = 1
) (
    input wire              clk,
    input wire              rst_n,
    input wire [WIDTH-1:0]  in_a, in_b,
    output reg [WIDTH-1:0]  out_c
);

always @(posedge clk or negedge rst_n)
    out_c <= in_a & in_b;

endmodule

Modue Instantiation

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Created Mar 10, 2020 // Last Updated Feb 27, 2023

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