Inst Encoding
Q&A
Reference 1
ISA instructions
MIPS encoding
MIPS-IV encoding:
I-Type (Immediate), 6 (op) + 5r + 5r + 16(i)
J-Type (Jump), 6 (op) + 26 (index)
R-Type (Register), 6 (op) + 5r + 5r + 5r + 5 (shift) + 6 (func)
CHERI MIPS encoding
ISAv7
Summary:
- all three-register-operand, non-memory-accessing CHERI-MIPS instructions using the following encodeing:
| Bit | size | value | |—–|——|——-| | 31-26 | 6 | 0x12 | | 25-21 | 5 | 0x00 | | 20-16 | 5 | r1 | | 15-11 | 5 | r2 | | 10-6 | 5 | r3 | | 5-0 | 6 | func |
All three-oprands non-mem instructions:
Two operands instructions:
One operands instructions:
CLoadTags rd, cb
| Bit | size | value | |—–|——|——-| | 31-26 | 6 | 0x12 | | 25-21 | 5 | 0x00 | | 20-16 | 5 | rd | | 15-11 | 5 | cb | | 10-6 | 5 | 0x1E | | 5-0 | 6 | 0x3F |
CClearTag cd, cb
| Bit | size | value | |—–|——|——-| | 31-26 | 6 | 0x12 | | 25-21 | 5 | 0x00 | | 20-16 | 5 | cd | | 15-11 | 5 | cb | | 10-6 | 5 | 0xB | | 5-0 | 6 | 0x3F |
CS[BHWD]: Store Integer via Capability
Part of integer register rs is stored to the memory location specified by cb.base + cb.offset + rt + 2^t * offset. Register cb must contain a capability that grants permission to store data. The t field determines how many bits of the register are stored to memory:
- 0 byte (8 bits)
- 1 halfword (16 bits)
- 2 word (32 bits)
- 3 doubleword (64 bits)
| Bit | size | value | |——-|—-|——–| | 31-26 | 6 | 0x3A | | 25-21 | 5 | rs | | 20-16 | 5 | cb | | 15-11 | 5 | rt | | 10-3 | 11 | offset | | 2 | 1 | 0 | | 1-0 | 2 | t |
CSC: Store Capability via Capability
CSC cs,rt,offset(cb)
CSCR cs,rt(cb)
CSCI cs,offset(cb)
Cap register cs is stored at the memory location of cb.base + cb.offset + rt + 16*offset
| Bit | size | value | |——-|—-|——–| | 31-26 | 6 | 0x3e | | 25-21 | 5 | cs | | 20-16 | 5 | cb | | 15-11 | 5 | rt | | 10-0 | 11 | offset |
- Cap Mode
References: More More
- reference ↩
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