Ibex
References:
RTL Coding
Main module is ibex_top, defined in ibex_top.sv
Core logic is split-out from the register file and RAMs under
ibex_top. This is to facilitate a dual-core lockstep implementation.
Register File
RegFile defined in rtl/ibex_pkg.sv
Three register file implementations, depending on different target technologies:
ibex_pkg::RegFileFF: flip-flop-based, default;ibex_pkg::RegFileLatch: latch-based;ibex_pkg::RegFileFPGA: for FPGA target;
Identification CSRs
Read-only CSRs, defined in rtl/ibex_pkg.sv, follows RISC-V Privileged Architecture.
mvendorid, 0 by default.marchid, 22 for ibex.mimpid, 0 by default.
Primitives Modules
Held outside rtl/ folder.
Can implement your own primitives.
Some primitives can be removed/ignored if not using in specific Ibex configurations.
Mandatory primitives:
prim_buf, a buffer used to avoid security critical logic being optimized away (by applying suitable constraints toprim_buf)prim_clock_gating, a clock gate.
Depends on configuration:
- see figure below.
More
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?