References:
Pointer Masking Feature of RISC-V: when enabled, the MMU will ignore the top N bits of the effective address. Then the application can use these top N bits in their own ways.
Most commonly, those bits are used to store various type of tags, which can be leveraged by a number of hardware/software features, including sandboxing mechanisms and dynamic safety checkers such as HWASAN.
This extension only adds the pointer masking functionality. Extensions that make use of the masked bits will be ratified independently and layered on top of the basic pointer masking functionality.
Effective address. As defined in the RISC-V Base ISA.
Masked bits. The top N bits of an address, where N is a configurable parameter (we will use N consistently throughout this document to refer to this parameter.)
Masked address. An effective address after the ignore transformation has been applied to it.
Address translation mode. As defined in RISC-V privileged specification. Could be Base, Sv39, Sv48, and Sv57.
Address canonicity. As defined in RISC-V privileged spec. Defined based on the privilege mode and address translation mode. Canonicity requirement:
NVBITS. The upper bits within an address that have no effect on addressing memory and are only used for canonicity checks. For example, in Sv48, these are bits 63-48.
VBITS. The bits within an address that affect which memory is addressed.
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?