Reference 1
Port: arguments/interfaces to other modules, contains input/output.
Parameter: constants. Typically used to specify the width of variables and time delays; has default value; can be overwritten during module instantiation.
https://www.chipverify.com/verilog/verilog-functions
For certain pieces of code to be repetitive and called multiple times within the RTL.
function [automatic] [return_type] name ([port_list]);
[statements]
endfunction
Starts with function, ends with endfunction.
Should have at least one input.
Return could be void (return nothing)
automatic will make the functino reentrant and items declared within the task are dynamically allocated rather than shared between different invocations of the task.
A Verilog module is a building block. It defines a design or testbench component. It does so by defining the building block’s ports and internal behaviour.
A module can be embedded into another module, creating hierachical designs.
Module & Components:
module and ends with endmoduleAllows a single piece of Verilog module code to be extensible and reusable.
Each instantiation of a Verilog module can supply different values to the parameters, creating different variations of the same base Verilog module.
For example, a FIFO Verilog module may have a Verilog parameter to adjust its data width (or even data type, in SystemVerilog).
A list of Verilog port (port list).
To communicate with other modules.
Ways to communicate other than ports: backdoors.
Item is essentially the code inside a module.
After port declaration.
Defines what constitutes the module, and can include many different types of declarations and definitions.
module my_module
#(
parameter WIDTH = 1
) (
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_a, in_b,
output reg [WIDTH-1:0] out_c
);
always @(posedge clk or negedge rst_n)
out_c <= in_a & in_b;
endmodule
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?