Example CSC

Q&A

  • How a store cap via cap instruction got implemented in a processor?

ISAv7

CSC: Store Capability via Capability

CSC cs,rt,offset(cb)
CSCR cs,rt(cb)
CSCI cs,offset(cb)

Cap register cs is stored at the memory location of cb.base + cb.offset + rt + 16*offset

| Bit | size | value | |——-|—-|——–| | 31-26 | 6 | 0x3e | | 25-21 | 5 | cs | | 20-16 | 5 | cb | | 15-11 | 5 | rt | | 10-0 | 11 | offset |

Decode

enq(ControlTokenT ct):

decodeInstruction(ControlToken i, MIPSReg rc, MIPSReg pc):

check i.inst: 4 categories: Immediate, Jump, Register, Coprocessor; return new control token di

Register .ri: check opcode ri.op (6 bits)

  • SPECIAL: decodeSpecial
  • SPECIAL2: decodeSpecial2
  • SPECIAL3: check func field ri.f
    • if ri.f is RDHWR: if rd is 0-14/29/30: opA=rc & 64'hFFFF
  • CP0: …

Coprocessor .ci: check opcode ci.op (6 bits)

  • COP1, COP3
  • COP2, LWC2, LDC2, SWC2 (0x3a), SDC2 (0x3e):
    • check cp2 enabled or not: cpEn.cu2: if zero will throw exception.
    • if COP2: check ci.cOp:
      • if CBTS, CBTU, CBEZ, CBNZ: reset the instruction type to be Immediate: di.inst = tagged Immediate unpack(pack(ci))
      • if CJALR: set second operand to be pc+8;
      • CClear:
        • create a mask of all ones;
        • cast instruction to immediate instruction;
        • check ci.r1 0/1/2/3: determine 15 registers to clear: 15-0/31-16 regular regs; or 15-0/31-16 cap regs. Update mask accordingly.
        • set first operand to be the mask value: di.opA = zeroExtend(mask)

Execute

input ControkTokenT di: enq(ControlTokenT di)

ouput ControlTokenT er: outQ.enq(er);, or pendingOps.enq(er);, or

Steps:

  • determine er.opA, er.opB
    • if di.opAsrc/di.opBsrc is RegFile: grab RegFile.regA/regB

  • determine er.storeData

    • if di.storeDatasrc is RegFile: RegFile.regB

  • pass opA, opB to coprocessor 1, get result and check exception.

  • determine er.archPC

  • prepare capReq:

    • if di.alu==Add: the offset set to be opA+opB
    • otherwise, capReq.offset is er.opB

  • Grab cap Response as capVal:

    • if di.alu==Cap, store capVal.data in calcResult.
    • er.opA = capVal.data;
    • if di.mem == Write and di.storeDatasrc == CoPro2, store er.storeData = capVal.storeData;

  • Parse di.alu: store result at calcResult.

    • Add,Sub,Or,Nor,Xor,And,SLT,SLTU,SLL,SRL,SRA.
    • Cop1:
    • FHi,FLo,Mul,Div,MulI,Madd,Msub,THi,TLo.

MemAccess

in/out ControlTokenT er/mi enq(ControlTokenT er)

Steps:

  • check address in bound: CoProResponse capResp <- capCop.getAddress()
  • Check whether cap access instruction:
    • er.inst matches tagged Coprocessor .ci &&&
    • er.memSize==CapWord
  • Take address from er.opA

  • check er.mem == Write

    • put in write.
    • if scResult, handle store conditional
      • if er.test==SC, set storeConditional = True;
      • Otherwise, memAccess write complete.
    • if not scResult, set er.mem = None

  • pass memory request down to dataMemory. Parameters:

    • mi.mem
    • addr
    • er.cop
    • er.storeData
    • er.memSize
    • er.test == LL,
    • cap,
    • er.id,
    • er.epoch,
    • er.fromDebug,
    • storeConditional

  • grab result from arith cap instructions that produce a late result

    • for alu instructions: mi.opA = capResp.data;
    • for branch instructions: mi.opB = capResp.data;

startMem

goes to dcache–l2cache–tagcontroller–memory.

Reference 1

  1. reference ↩
Created Jun 6, 2020 // Last Updated May 18, 2021

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