ICache

Todones


CacheInstIfc (in MIPS.bsv)
- put() -> rule doPut() // 
- getRead()
- invalidate()
- getConfig()
- getResponse() //
- interface Master#

Q&A

  • Who calls this module and what is the input?

    • called from Memory.bsv: rule feedICache, after TLB translation. iCache.put(req);
    • The input is the physical memory access request req of type CacheRequestInstT.
    • see Memory.bsv.

  • Where does it go?

    • it send a memory request to CacheCore, iCache.put(req); see CacheCore.
    • it returns the response back to Memory.bsv: interface InstMemory:getResponse. CacheResponseInstT resp <- iCache.getRead();
    • The response then forwarded to Scheduler.bsv: mkScheduler: method enq(): CacheResponseInstT instResp <- m.getInstruction();

  • Where to fetch the tag and attach it to the instruction?

Reference 1

Connections

// Memory.bsv
mkConnection(iCache.memory, theMemMerge.slave[0]);
mkConnection(dCache.memory, theMemMerge.slave[1]);

States

FIFO#(CacheResponseInstT)          preRsp_fifo <- mkLFIFO;
FIFO#(CheriPhyByteOffset)                addrs <- mkLFIFO;
Reg#(CacheRequestInstT)              reqInWire <- mkWire;
FIFOF#(Bool)                      nextFromCore <- mkLFIFOF;
//FIFOF#(Bool)                        returnNext <- mkUGSizedFIFOF(4); // Lots of room due to being unguarded.
FF#(CheriMemRequest, 2)                memReqs <- mkUGFF();
FF#(CheriMemResponse, 2)               memRsps <- mkUGFF(); // If this FIFO has capacity for less than 4 (the size of one burst response) the system can wedge on a SYNC when the data interface stalls waiting for all responses.
CacheCore#(2, Indices, 1)                 core <- mkCacheCore(cacheId, WriteThrough, OnlyReadResponses, InOrder, ICache, 
                                                            zeroExtend(memReqs.remaining()), 
                                                            ff2fifof(memReqs), ff2fifof(memRsps));
Reg#(CheriTransactionID)        transactionNum <- mkReg(0);
Reg#(PhyAddress)                lastInvalidate <- mkRegU;

interface CacheInstIfc

method getRead()

method ActionValue#(CacheResponseInstT) getRead()

  • grab one resp from preRsp_fifo
  • grab one addr from addrs

test_cp2_ccall.log

debug with icache tagcontroller taglookup

first instruction from start: 0x4000.0000; line number (cut 5-bits): 0x0200.0000

icache-> flit=BYTE_4, l2cache->tagcontroller-> taglookup & memory <- MemoryResponse with tag and 64-bit data.

byte addr line num offset tagTb byte addr tagTb line num offset
0x4000.0000 0x0200.0000 00 0x3fff.f000 0x0.01ff.ff80 00
  1. tagController:
    • send mem request:
    • send tag request to tag cache (BYTE_4), if tag cache miss, forward the req to memory(BYTE_32): taglookup: received request Read MemoryRequest; Injecting request from tag lookup engine
  2. tagController: get mem response, get tag response.
  1. reference ↩
Created May 27, 2020 // Last Updated May 18, 2021

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