MemAccess.bsv

Reference 1

Memory access stage of the pipeline

//cheri/trunk/MemAccess.bsv
module mkMemAccess#(
  DataMemory m
  `ifdef USECAP
    , CapCopIfc capCop
  `endif
)(PipeStageIfc);

Overview

Input:

  • DataMemory m. The memory hierachy which needs the system control processor for TLB integration
  • CapCopIfc capCop.

Methods:

  • enq (ControlTokenT er)
  • first
  • deq
  • clear // should never be called

method Action enq(ControlTokenT er)

Input: ControlTokenT er Output: ControlTokenT mi. // outQ.enq(mi) // mi has the updated

Steps:

  • Call capCop.getAddress(), check exception. getAddress() is defined in CapCop.bsv; it will check the length violation for the capability being used.

  • check alignment of memory

  • ??? L86-88, L140-156, scResult er.test er.opB[0]==1'b1 ??? what is those used for? Choose a value of mi.mem from Write/None, and set storeConditional?

  • m.startMem(mi.mem, addr, er.cop, er.storeData, er.memSize, er.test==LL, cap, er.id, er.epoch, er.fromDebug, storeConditional);

    • mi.mem: Read/Write/None
  1. reference ↩
Created Apr 4, 2020 // Last Updated May 18, 2021

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the fundmental principles of
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to improve security...

... what would you change?