Scheduler.bsv

//cheri/trunk/Scheduler.bsv

// The mkScheduler module does a "pre-decode" of the instruction to find which
// register numbers may be fetched and to classify the branch behaviour of the
// instruction for the branch predictor.
module mkScheduler#(
  // The scheduler needs the branch interface so that it can report the branch type
  // for the next prediction.  This saves the branch predictor from having to guess
  // if the next instruction is a branch or not.
  BranchIfc branch,
  // The scheduler needs the register file interface because it submits the
  // register fetches that are retrieved in the decode stage.
  MIPSRegFileIfc theRF,
  // The scheduler needs the CP0 interface because it also submits potential register
  // reads to the CP0 interface, which are also retrieved in the decode stage.
  CP0Ifc cp0,
  CoProIfc cop1,
  `ifdef USECAP
    CapCopIfc capCop,
  `endif
  // The scheduler needs the instruction memory interface because it pulls the next
  // instruction out of the instruction memory to begin pre-decode analysis.
  InstructionMemory m
  // The scheduler exports a PipeStageIfc interface, (a FIFO#(ControlTokenT) interface),
  // for integration with the pipeline.
  `ifdef STATCOUNTERS
  , StatCounters statCounters
  `endif
)(PipeStageIfc);