Instructions
RISC-V Instructions
Instructions dependent on encoding modes
More
- Csc
- CGet/SetDefault
(ISAv7: Ch 7, p240) Format CSC cs, rt, offset(cb) CSCR cs, rt(cb) CSCI cs, offset(cb) Capability register cs is stored at memory location [cb.base + cb.offset + rt + 16 * offset], and the bit in the tag memory associated with this address is set to the value of cs.tag. Capability cb must contain a capability that grants permission to store capabilities. The virtual address of [cb.base + cb.offset + rt + 16 * offset] must be capability_size aligned.
(ISAv7, ch7.5) CGetDefault and CSetDefault get and set the capability register that is implicitly employed by the legacy MIPS load and store instructions. In the current version of ISA, this register is special-purpose capability register 0. # The following are equivalent: CGetDDC $c1 CGetDefault $c1 CReadHWR $c1, $0 # The following are equivalent: CSetDDC $c1 CSetDefault $c1 CWriteHWR $c1, $0
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?