References:
References: target/mips/translate.c // target/mips/translate.c mips_tr_translate_insn() --> gen_branch() // is_slot decode_opc() --> gen_compute_compact_branch() --> gen_branch() // bcond_compute == 0 --> gen_helper_copy_cap_btarget_to_pcc(cpu_env) // MIPS_HFLAG_BRCCALL/MIPS_HFLAG_BRC --> CHERI_HELPER_IMPL(copy_cap_btarget_to_pcc(CPUArchState *env)) More
References: target/mips/translate.c mips_tr_translate_insn() --> decode_opc() // !(ctx->hflags & MIPS_HFLAG_M16) --> decode_opc_special() --> generate_exception_end(ctx, EXCP_SYSCALL) generate_exception_end() -> generate_exception_err() // target/mips/translate.c // generate_exception_end(ctx, EXCP_SYSCALL) --> generate_exception_err(ctx, excp, 0) static inline void generate_exception_err(DisasContext *ctx, MipsExcp excp, int err) { TCGv_i32 texcp = tcg_const_i32(excp); TCGv_i32 terr = tcg_const_i32(err); save_cpu_state(ctx, 1); gen_helper_raise_exception_err(cpu_env, texcp, terr); tcg_temp_free_i32(terr); tcg_temp_free_i32(texcp); ctx->base.is_jmp = DISAS_NORETURN; } More
Tracking the implementation of branch instructions in MIPS target. References: target/mips/translate.c Branches is translated in function gen_compute_branch: gen_compute_branch // target/mips/translate.c /* Branches (before delay slot) */ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int insn_bytes, int rs, int rt, int32_t offset, int delayslot_size) { target_ulong btgt = -1; int blink = 0; int bcond_compute = 0; TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); // Note: For CHERI btgt is an absolute address not an offset relative // to PCC.
Q&A Where is the DDC check during legacy ld/st? Reference reference check_cap Who call it? target_ulong check_ddc(CPUArchState *env, uint32_t perm, uint64_t ddc_offset, uint32_t len, uintptr_t retpc) void CHERI_HELPER_IMPL(ddc_check_bounds(CPUArchState *env, target_ulong addr, target_ulong num_bytes)) target_ulong CHERI_HELPER_IMPL(pcc_check_load(CPUArchState *env, target_ulong pcc_offset, MemOp op)) void CHERI_HELPER_IMPL(raise_exception_ddc_perms(CPUArchState *env, uint32_t required_perms)) void CHERI_HELPER_IMPL(raise_exception_ddc_bounds(CPUArchState *env, target_ulong addr, uint32_t num_bytes)) void CHERI_HELPER_IMPL(ccheck_load_pcrel(CPUArchState *env, target_ulong addr, uint32_t len)) ddc_check_bounds ddc_check_bounds caller _generate_ddc_checked_ptr, and upper callers:
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?