Reference: Cpu0 – Global Variables
The global variable DAG translation is different from local variable ones. It creates IR DAG nodes at run time in backend C++ code according to
llc -relocation-modeloption while the other DAG just do IR DAG to Machine DAG translation directly according to the input file of IR DAGs(except the Pseudo instruction REtLR used in Chapter 3_4).
Just like Mips, Cpu0 supports both static and pic mode:
relocation-model=pic: (default) Use position independent address.relocation-model=static: Use absolute address.Two different layouts of global variables for each mode:
-cpu0-use-small-section=false: (default) Will be put in .data or .bss, 32 bits addressable.-cpu0-use-small-section=true: .sdata or .sbss, 16 bits addressable.When relocation-model=static:
| option: cpu0-use-small-section | false | true |
|---|---|---|
| addressing mode | absolute | $gp relative |
| addressing | absolute | $gp + offset |
| Legalized selection DAG | (add Cpu0ISD::Hi |
(add register %GP, Cpu0ISD::GPRel |
| Cpu0 | lui $2, %hi(gl); ori $2, $2, %lo(gl); |
ori $2, $gp, %gp_rel(gl); |
| relocation records solved | link time | link time |
relocation-model is used to generate either Absolute Addressing or Position Independent Addressing. The exception is -relocation-model=static and -cpu0-use-small-section=false. In this case, Cpu0 uses $gp relative addressing in this mode.When relocation-model=pic:
| option: cpu0-use-small-section | false | true |
|---|---|---|
| addressing mode | $gp relative | $gp relative |
| addressing | $gp + offset | $gp + offset |
| Legalized selection DAG | (load (Cpu0ISD::Wrapper register %GP, |
(load EntryToken, (Cpu0ISD::Wrapper (add Cpu0ISD::Hi |
| Cpu0 | ld $2, %got(gl)($gp); |
lui $2, %got_hi(gl); add $2, $2, $gp; ld $2, $got_lo(gl)($2); |
| relocation records solved | link/load time | link/load time |
Chapter6_1/Cpu0MCInstLower.cpp
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?