LLVM has its test cases (regression test) for each backend to verify the backend compiler without implementing any simulator or real hardware platform.
regression test for arch in ./llvm/test/src/test/CodeGen/
To run:
cheri# pwd
/root/cheri/llvm-project/llvm/test/CodeGen/Mips/cheri
cheri# /llvm-build-bin/llvm-lit cheri-sandbox-vaargs.ll
llvm-lit: /root/cheri/llvm-project/llvm/utils/lit/lit/llvm/config.py:317: note: Running tests for CHERI_CAP_SIZE=16
llvm-lit: /root/cheri/llvm-project/llvm/utils/lit/lit/llvm/config.py:405: note: using clang: /root/sva/cheri/bsd112_sync_root/root/cheri/build/llvm-project-build/bin/clang
llvm-lit: /root/cheri/llvm-project/llvm/utils/lit/lit/llvm/subst.py:127: note: Did not find llvm-exegesis in /root/sva/cheri/bsd112_sync_root/root/cheri/build/llvm-project-build/./bin
llvm-lit: /root/cheri/llvm-project/llvm/utils/lit/lit/llvm/subst.py:127: note: Did not find llvm-mca in /root/sva/cheri/bsd112_sync_root/root/cheri/build/llvm-project-build/./bin
llvm-lit: /root/cheri/llvm-project/llvm/utils/lit/lit/llvm/subst.py:127: note: Did not find llvm-rc in /root/sva/cheri/bsd112_sync_root/root/cheri/build/llvm-project-build/./bin
-- Testing: 1 tests, 1 workers --
PASS: LLVM :: CodeGen/Mips/cheri/cheri-sandbox-vaargs.ll (1 of 1)
Testing Time: 0.31s
Expected Passes : 1
cheri#
Regression test file:
once backend compiler changed, the regression test cases guard the changes has no side effect or bugs for other parts of backend program.
// llvm/test/CodeGen/Mips/setule.ll
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-p
refix=16
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileC
heck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@l = global i32 20, align 4
@m = global i32 10, align 4
@r1 = common global i32 0, align 4
@r2 = common global i32 0, align 4
@r3 = common global i32 0, align 4
define void @test() nounwind {
entry:
%0 = load i32, i32* @j, align 4
%1 = load i32, i32* @k, align 4
%cmp = icmp ule i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $[[REGISTER:[0-9]+]], $24
; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp ule i32 %2, %1
%conv2 = zext i1 %cmp1 to i32
store i32 %conv2, i32* @r2, align 4
ret void
}
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?