.got addressing?References:
Tasks for LLVM Machine Representation:
Pass manager pipeline is setup in TargetPassConfig.
insertPass and subtitutePass.MachineInstruction MIMachineOperand MOPMCInstrDesc: Opcode/Instruction DescriptionMachineBasicBlock (MBB)MachineFunction (MF)Function, TargetMachine, TargetSubtargetInfo, MCContext, …MachineRegisterInfo maintains list of uses and definitions per register.MachineRegisterInfo
.isVirtualRegister(Reg), .isPhysicalRegister(Reg)Register == 0: no register used.TargetFrameLowering class
class TargetFrameLowering { // ...
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
virtual void emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const = 0;
virtual void emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const = 0;
virtual void determineCalleeSaves(MachineFunction &MF, BitVector /*...*/);
virtual void processFunctionBeforeFrameFinalized(MachineFunction /*...*/);
}
References: llvm/lib/CodeGen/MachineFunctionPass.cpp llvm/include/llvm/CodeGen/MachineFunctionPass.h Pass definition and creation /// MachineFunctionPass - This class adapts the FunctionPass interface to /// allow convenient creation of passes that operate on the MachineFunction /// representation. Instead of overriding runOnFunction, subclasses /// override runOnMachineFunction. classMachineFunctionPass : public FunctionPass { public: bool doInitialization(Module&) override { // Cache the properties info at module-init time so we don't have to // construct them for every function.
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?