References:
Target dependent implementation of prologue/epilogue emission.
See [../] for callers.
Adjust stack pointer:
MipsSEFrameLowering::emitPrologue()
=> TII.adjustStackPtr(SP, -StackSize, MBB, MBBI)
MipsSEInstrInfo::adjustStackPtr()
=> BuildMI // addi sp, sp, amount
The instruction to spill return address $ra register is built here.
// search Mips::RA_64, spill RA as callee saved reg
MipsSEFrameLowering::spillCalleeSavedRegisters(){
//...
DebugLL("before spill callee save: block: "; MBB.dump(););
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
// ...
// Insert the spill to the stack frame.
bool IsKill = !IsRAAndRetAddrIsTaken && KillRAOnSpill;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
CSI[i].getFrameIdx(), RC, TRI);
}
DebugLL("done spill callee save: block: "; MBB.dump(););
}
//
// in file llvm/lib/Target/Mips/MipsISelLowering.cpp
//
MipsTargetLowering::lowerRETURNADDR()
=> unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); // add live-in for RA.
If you could revise
the fundmental principles of
computer system design
to improve security...
... what would you change?